(a) Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a thin film capacitor having an MIM (Metal/Insulator/Metal) structure.
(b) Description of the Related Art
Recently, in the field of analog circuits requiring high-speed operation, a semiconductor device having higher capacity has being developed. Generally, in case a capacitor has a PIP structure where a polysilicon layer, an insulator layer, and a polysilicon layer are laminated, there is a disadvantage that, as the upper electrode and the lower electrode use conductive polysilicon, oxidation occurs in the interfaces between the electrodes and a dielectric thin film so that natural oxide is formed and thus total capacitance falls.
To solve the disadvantage, the structure of the capacitor has been changed into an MIS (Metal/Insulator/Semiconductor) structure or an MIM structure. Then, the MIM structure thereof has low resistivity and no parasitic capacitance due to depletion therein, such that it is mainly used in high performance semiconductor devices.
Conventional arts related to thin film capacitors are disclosed in U.S. Pat. Nos. 6,436,787; 6,426,250; 6,387,775; 6,271,084; and 6,159,793.
Then, a method of fabricating a thin film capacitor having the conventional MIM structure will be briefly described. FIG. 1 is a cut view showing a thin film capacitor having the conventional MIM structure.
In order to fabricate a capacitor having such conventional MIM structure, first, conventional semiconductor fabricating processes are carried out over a semiconductor substrate 1, and then a lower insulating film 2 is formed.
Next, lower metal wiring 3, a dielectric layer 4, and upper metal wiring 5 are formed on the lower insulating film 2 in order.
Herein, the lower metal wiring 3 corresponds to a first electrode layer of the MIM capacitor, and the upper metal wiring 5 corresponds to a second electrode layer of the MIM capacitor.
Then, the upper metal wiring 5 is selectively etched to have a predetermined width, and then the dielectric layer 4 and the lower metal wiring 3 are selectively etched to have a predetermined width.
As described above, capacitance of the conventional MIM capacitor depends on the size of the upper metal wiring 5.
Then, with higher integration of semiconductor devices, the size of the device has been reduced, such that the size of the upper metal wiring comes to be small. Thus, in order to maintain capacitance with no reduction, while the depth of the dielectric layer or the total size is reduced, various methods for increasing the size between metals with reduced have been researched. Such methods are to improve operating speed by increasing the coupling ratio to ensure capacitance.
However, such methods of increasing the coupling ration with maintaining the capacitance come to reach the limitations, and thus new methods are urgently required.